The present invention relates to integrated microelectromechanical systems and, more particularly, to the monolithic integration of microelectronic circuitry with microelectromechanical devices on the same substrate or chip.
Integrated microelectromechanical systems (iMEMS) combine microelectromechanical device structures with on-chip electronic circuitry. This integration can improve performance, reliability, and functionality and reduce size and cost over standard MEMS devices. For example, monolithic integration may reduce the number of input-output (I/O) bondpads required for electrical switching in a complex structure, improve the driving and control of microactuators, improve the amplification and/or processing of sensory signals generated by microsensors by reducing stray capacitance and sensitivity to noise, minimize die area, and enable batch fabrication. Furthermore, the high speed, dense switching enabled by on-chip integrated circuitry (e.g., a metal-oxide semiconductor field effect transistor, or MOSFET) cannot be achieved in micromechanical relays that are frequently used to switch MEMS devices. In particular, the reliability of MOSFET circuitry is well understood, whereas micromechanical relays are still being developed.
On-chip circuitry is particularly advantageous when used to control and drive complex MEMS devices, such as the Polychromator used for spectral identification. U.S. Pat. No. 5,905,571 to Butler et al. The Polychromator comprises an electrostatically actuated programmable diffraction grating with 1024 individually addressable diffractive elements. To actuate all of these diffractive elements independently presently requires an equal number of I/O bondpads hard-wired to a power source. This complex circuitry can have a deleterious effect on device yield and reliability. It is estimated that the number of wire bonds can be substantially reduced, perhaps to as few as 20-30 bondpads, by controlling the diffractive elements with on-chip electronic circuitry.
However, monolithic integration of electronic circuitry with a MEMS device presents serious materials and process compatibility challenges. A number of approaches have been developed to integrate electronic circuitry with a MEMS device on the same chip. U.S. Pat. No. 5,326,726 to Tsang et al. discloses an interleaved or merged process approach for fabricating a monolithic chip containing integrated circuitry interconnected to a microstructure (i.e., a MEMS device). The approach of Tsang et al. requires that the separate steps for forming the MEMS device and the integrated circuit be interleaved for compatibility, with the electronic circuitry being formed at least in part prior to the MEMS device, and electrical interconnections between the circuitry and the MEMS device being formed thereafter. While Tsang et al. use some essentially standard process steps, other process steps must be modified due to conflicting requirements between the circuitry and the MEMS device. The method of Tsang et al. comprises 67 processes which are further broken down into approximately 330 process steps.
Modification and interleaving of the process steps may significantly decrease the circuit performance and the overall process yield. These modified process steps are primarily dictated by thermal cycles and topography during processing. For example, MEMS devices frequently have severe topography, with structures extended several microns up from the substrate. This severe topography may require modifications to photolithography and etching processes for forming the electrical interconnections between the MEMS device and circuitry. In addition, a high-temperature annealing step is required to relieve stress in surface micromachined MEMS devices that use low-pressure chemical vapor deposition (LPCVD) of polysilicon as the structural material. This high-temperature annealing step may cause unwanted diffusion of dopants in the electronic circuitry. Furthermore, the high-temperature step necessitates refractory (e.g., tungsten) interconnect metallizations in place of traditional aluminum-metallized CMOS circuitry.
Many of these process modifications can be eliminated by substantially separating the process steps for the MEMS device from the process steps for fabricating the electronic circuitry, thereby allowing the use of standard process steps as known to the art, especially for fabricating the electronic circuitry. In a post-CMOS process, the MEMS device is fabricated after the electronic circuitry. Fabricating the circuitry first and then depositing and patterning the structural polysilicon avoids the problem with large topographical variations of the MEMS device structures from affecting the lithography for fabricating the circuitry, but severely limits the thermal budget for the MEMS device fabrication to that acceptable for the electronic circuitry. This restricted thermal budget can necessitate process and material property modifications from conventional surface micromachining processing and materials.
Alternatively, the MEMS device can be fabricated before the electronic circuitry. A pre-CMOS method of separating the process steps is disclosed in U.S. Pat. No. 5,798,283 to Montague et al., and U.S. Pat. No. 5,963,788 to Barron et al., which are incorporated herein by reference. The MEMS device can be fabricated within a shallow trench in a first portion of the substrate and encapsulated with a sacrificial material (e.g., silicon dioxide or a silicate glass). This embedded polysilicon microstructure allows the MEMS device to be annealed and the substrate planarized (e.g., by chemical-mechanical polishing) prior to fabricating the electronic circuitry on a second portion of the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the MEMS device can be released for operation by etching away the encapsulating sacrificial material. By fabricating the MEMS device prior to the electronic circuitry, this pre-CMOS method avoids subjecting the electronic circuitry to the high-temperature annealing step required to stress relieve the MEMS device. Consequently, standard CMOS process steps and uncomplicated lithography can be used. However, this method still requires many photolithographic masks (e.g., 25-30) and process steps (e.g., 500), because it requires separate fabrication processes for the MEMS device and the electronic circuitry.
A need still exists for a simple method to monolithically integrate a MOSFET with a MEMS device on a single chip. The present invention provides a simple method for iMEMS fabrication by taking advantage of the long, high-temperature annealing step of the MEMS process to provide for dopant diffusion to create the source and drain regions of a MOSFET. In effect, the present invention provides a means to use the MEMS process to create MOSFETs, thereby eliminating many process steps.
The method of the present invention for integrating a MOSFET with a MEMS device on a substrate comprises forming a gate insulator of the MOSFET on an electronics portion of the substrate; forming a gate electrode of the MOSFET on the gate insulator; forming an inter-layer dielectric on the electronics portion of the substrate, thereby encapsulating the gate electrode and the gate insulator, forming a gate electrical contact through the inter-layer dielectric to the gate electrode; forming a source electrical contact through the inter-layer dielectric to a source region of the substrate proximate to one side of the gate electrode wherein the source electrical contact further comprises a solid dopant source; forming a drain electrical contact through the inter-layer dielectric to a drain region of the substrate proximate to the other side of the gate electrode wherein the drain electrical contact further comprises a solid dopant source; forming a MEMS device structure on a MEMS portion of the substrate comprising at least one dielectric layer on the substrate, at least one structural layer built up from the at least one dielectric layer, and at least one sacrificial layer interleaving the at least one structural layer; heating the substrate to a sufficiently high temperature to thermally diffuse the dopant atoms from the source and drain electrical contacts into the substrate to form the source and drain of the MOSFET; forming electrical interconnections from the gate electrical contact, the source electrical contact, and the drain electrical contact of the MOSFET to the MEMS device structure; and removing the at least one sacrificial layer to release the MEMS device.
The gate insulator of the MOSFET can be formed simultaneously with the dielectric layer of the MEMS device. The gate electrode of the MOSFET can be formed simultaneously with a first structural layer of the MEMS device. Furthermore, the electrical contacts of the MOSFET can be formed from another structural layer of the MEMS device. Typically, the gate electrode and electrical contacts of the MOSFET and the structural layers of MEMS device can be doped polysilicon. Preferably, the thermal diffusion step can also thermally anneal the stress in the structural layers of the MEMS device. An nMOSFET can be formed in a p-type substrate or a p-type well using a donor atom as the thermally diffused dopant to form the source and drain. Alternatively, an n-type substrate can be used with an acceptor dopant to form a pMOSFET.
The present invention further comprises an integrated microelectromechanical system, comprising at least one MOSFET on an electronics portion of a substrate, further comprising a gate insulator on the substrate, a gate electrode on the gate insulator, a dopant-diffused source in the substrate proximate to one side of the gate electrode, a dopant-diffused drain in the substrate proximate to the other side of the gate electrode, an inter-layer dielectric on the electronics portion of the substrate that encapsulates the gate electrode and the gate insulator, a gate electrical contact through the inter-layer dielectric to the gate electrode, a source electrical contact through the inter-layer dielectric to the source, a drain electrical contact through the inter-layer dielectric to the drain; and at least one MEMS device on a MEMS portion of the substrate, further comprising at least one dielectric layer on the substrate and at least one structural layer built up on the at least one dielectric layer; and electrical interconnections from the gate electrical contact, source electrical contact, and drain electrical contact of the at least one MOSFET to the at least one MEMS device.